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Circuit underutilization : ウィキペディア英語版 | Circuit underutilization ''Not to be confused with Circuit minimization for Boolean functions, which is logical optimization rather than physical.'' Circuit underutilization also programmable circuit underutilization, gate underutilization, logic block underutilization refers to a physical incomplete utility of semiconductor grade silicon on a standarized mass-produced circuit programmable chip, such as a gate array type ASIC, an FPGA, or CPLD. ==Gate array== In the example of a gate array, which may come in sizes of 5,000 or 10,000 gates, a design which utilizes even 5,001 gates would be required to use a 10,000 gate chip. This inefficiency results in underutilization of the silicon.〔http://chipdesignmag.com/display.php?articleId=386〕
抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)』 ■ウィキペディアで「Circuit underutilization」の詳細全文を読む
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